Exhibitor Seminars
TSN6
Interpreter
TechSTAGE NORTH, East Hall 5, TOKYO BIG SIGHT
15:10-16:50 Thu., 14-Dec
STS Advanced Lithography Session(2)
Emerging Patterning Technology and Related Metrology
Sponsored by
Session Description
The presenters will share the latest on topics including multielectron beam exposure technology, nano-imprinting, and pattern measurement technologies.
Program Agenda
Naoya Hayashi Dai Nippon Printing Co., Ltd.
Hisanobu Azuma Canon Inc.
15:10-15:40
Development of Multi-beam Mask Writer with Inline Mask Process Correction
Noriaki Nakayamada
Senior Technology Expert
Mask Lithography Engineering Department
NuFlare Technology Inc.
Due to the introduction of EUV and ILT lithography, the density and complexity of the mask patterns have already surpassed the capability limit of conventional variable shaped beam writer in terms of both accuracy and throughput. Multi-beam mask writer is expected to make a significant breakthrough in the mask making technology, not solely in writing but also in data preparation. We will give a tutorial about technical hurdles to be overcome in developing a multi-beam mask writer and will share the latest performance results obtained by then. We will also present the development status of our new datapath enabling inline mask process correction (MPC), which has been only realized by the introduction of multi-beam mask writer.
15:40-16:10
Progress and Perspective of Nano Imprint Lithography for Production in Semiconductor Devices
Tatsuhiko Higashiki
Senior Fellow
Process Technology R&D Center
Toshiba Memory Corp.
We have been studying nanoimprint lithography called NIL that print device patterns on the template to silicon wafer directory. NIL had some subjects such as overlay accuracy and defect control. In this paper, I will talk about Progress and Perspective of nano iprint lithography for production in semiconductor devices.
16:10-16:40
SEM based metrologies corresponding to diversification of Semiconductor device -Cutting edge metrology solutions with using CD-SEM
Takeshi Kato
Senior Engineer
Electronic Device Systems Business Group
Hitachi High-Technologies Corp.
Device feature sizes have been shrunk to 1/100 exponentially for these 30 years just as the prediction of Moor’s rule for semiconductor integration and transistor performance. Corresponding to diversification of device pattern features, CD-SEM based metrologies have been applied as an indispensable item to data collection in research field and quality control in manufacturing of semiconductor wafers. In this presentation, we introduce cutting edge SEM based metrologies and process control for small feature size of dense patterns, overlay, fidelity of 2D patterns and edge roughness.