Exhibitor Seminars
ETSE30
Hall 3, 4F, West Exhibition Hall, Tokyo Big Sight
12:40-13:30 Thu., 12-Dec
SMART Transportation supported by latest JISSO technologies, will need new design methodologies
Sponsored by
Session Description
By a factor of increased development costs for the miniaturization of semiconductor, technology be implemented in three dimensions to connect the chips in a package by dividing the chip is accelerating. Various manufacturing methods/materials/assembly technologies have emerged, and the role and design method of packages are about to change drastically. To introduce the SoC/PKG/PCB co-design environment due to the CR-8000 Design Force.
Program Agenda
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